Checking whether signal is asserted for minimum clock cycles

[user60]

In reply to ben@SystemVerilog.us:

Good point. How about

a_min_32_clk_low : assert property (@(posedge clk)
                      ##1 $fell(a) |-> !a[*32]);

OP has to confirm whether this will satisfy his need.

Srini
http://www.verifworks.com