In reply to raghav kumar:
The issue is that you’re dealing with real numbers, thus the “==” is not going to work because of resolution.
You’ll need to specify a range of acceptable accuracy. Below is code that worked, but you need to set the acceptable ranges and timescales, using the timeunit and timeprecision
module m2b;
timeunit 1ns; timeprecision 100ps;
realtime clk_period =1000.0/340.0ns; // =2.941176470588235
bit clk, RESET_N, ENABLE;
property T_clk(real clk_period);
time current_time;
// disable iff(!RESET_N || !ENABLE)
(('1,current_time=$realtime) |=>
(clk_period <= $realtime-(current_time-0.001ns)) ||
(clk_period >= $realtime-(current_time + 0.001ns)));
endproperty
assert_period:assert property (@(posedge clk)T_clk(clk_period))
$display("%t TB_INFO : clk correct",$realtime);
else
$warning("%t TB_INFO : clk not correct",$realtime);
initial forever #1.470 clk=!clk;
initial begin
$display("START");
repeat(10) @(posedge clk);
// $display("%t %t TB_INFO : clk correct",$realtime, $realtime);
$finish;
end
endmodule : m2b
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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