Checking clock period using system verilog assertion

SystemVerilog
,
2

The issue here is that the formal argument of the property is of type “int”, yet you’re passing as actual a realtime. Per 1800
“integer_atom_type ::= byte | shortint | int | longint | integer | time
non_integer_type ::= shortreal | real | realtime”
The following code worked OK

module m2b; 
	time clk_period =20.0/1.0ns;
	bit clk, RESET_N, ENABLE;
	property T_clk(int clk_period);
		realtime current_time;
		// disable iff(!RESET_N || !ENABLE)
		(('1,current_time=$realtime) |=>(clk_period==$realtime-current_time));
    endproperty
 
    assert_period:assert property (@(posedge clk)T_clk(clk_period))
	   $display("%t TB_INFO : clk  correct",$realtime); 
       else
	   $warning("%t TB_INFO : clk not correct",$realtime);
    initial forever #10 clk=!clk; 
    initial begin 
	  $display("START");
	  repeat(10) @(posedge clk); 
	  $finish; 
    end
endmodule : m2b