In reply to ben@SystemVerilog.us:
Hi All,
When I run the above code in VCS I am getting the following error please let me know any switches in the command line to be used. Or if this should be run using specific version of vcs(I am using version 2013 of vcs).
Error-[SVA-ITRHS] Invalid type in local variable assign
clock_generate_assert.sv, 6
clock_assert, “$realtime”
Expressions involving real, realtime, string, event and dynamic
SystemVerilog types including virtual interface references are not allowed
in local variable assignments in properties and sequences.
Regards,
Rajesh.B