In reply to ben@SystemVerilog.us:
“If it is easier for you to build and integrate the DUT_TLM in VHDL then do so.”
Agreed. I would prefer SV for my models, if starting from scratch ( for several reasons ). We haven’t used SV for design before; perhaps we should consider it.
" I would not even consider VHDL, but may consider C++ as an addendum"
Do you mean SV for design AND C++, or, designing in purely C++ and have some translation tool (to HDL)? I’ve heard those tools can produce unwieldy results, but I have no experience with them.
"I would say YES. The UVM verification model may ncorporate a scoreboard with a buffer memory (or an associative array or a queue) to sync up transactions and checkers. Does tis make sense to you? "
If you just mean a scoreboard with say, FIFOs for expected & actual transactions, then yes.
“a checker that may (not sure if this is really needed, but maybe) emulate the main characteristics of the chip.”
What is your thinking behind this; that emulating the characteristics of the chip may NOT be required?
Finally, about assertions. I am not currently at the experience level with assertions that I want to be. The only place I use them is in the interface, to monitor the protocol is obeyed. Beyond that, where are the primary places they offer the most benefit? (I havent gotten time to read your book yet!)
- design (bound in, because our design is VHDL)
- protocol checkers
… ?