In reply to bmorris:
[quote]In reply to ben@SystemVerilog.us:
Just to be clear, in your suggested approach, the DUT TLM is captured in SV (not VHDL), in the UVM environment. /quote]
If it is easier for you to build and integrate the DUT_TLM in VHDL then do so.
In the world of design and verification, I started with VHDL and wrote 6 books about the use of VHDL for design and verification. However, when I got involved with SystemVerilog and assertions, and looking at the current progress and features of SystemVerilog compared to VHDL, I see far, far more strengths in SystemVerilog, and I abandoned VHDL. In fact, if I were to start a new design and verification project, I would not even consider VHDL, but may consider C++ as an addendum. Anyway, this is why I picked that DUT TLM in SystemVerilog, but you should do what is right for you.
I would say YES. The UVM verification model may ncorporate a scoreboard with a buffer memory (or an associative array or a queue) to sync up transactions and checkers. Does tis make sense to you?
Again, and just for the record, are you using assertions in your design and in your interfaces? They can save you a lot of time! I have said this before, and I’ll say it again : An assertion is a statement that the property is true. Everytime you do a verification model (UVM or other), you are indeed writing assertions. Assertions can be written with code and with an assertion language like SVA. There is nothing magical about SVA; the only exception is that SVA assertions are concice, and can quickly be written, and tools help in the fast detection of errors and in the application of coverage (that certain sequences or properties were covered).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115