In reply to ben@SystemVerilog.us:
Just to be clear, in your suggested approach, the DUT TLM is captured in SV (not VHDL), in the UVM environment. There is a pin-wiggle to transaction barrier now; therefore, the model must be awaiting for sometimes partial bus transactions to occur (like a read), and must then complete the bus activity (like how a responder sequence works), directly through an interface call.
Is this an accurate description?