In reply to ben@SystemVerilog.us:
This is what I said, there are areas where you should use assertion checkers. These FSM - a counter is a simple FSM - and interfaces like UARTs.
To give you an example from my professional life: We had to verify an image processing chip to verify with a lot of algorithmic stuff inside. There was C++ model available (several thousands lines of code). We used this as reference model in a scoreboard. You’ll never have a chance to verify this behavior with assertions only.
Christoph Suehnel