In reply to bmorris:
Regarding a reference model you cannot give clear advice to use a SV or any other model. What you are using depends on 2 things. Firstly, what is available. Do system architects have C++ models or is a behavioral model in VHDL or SV available. Or do we have any other reference like a Matlab model. Secondly it has to be a model which represents exactly the function of the DUT. Exactly means in terms of FUNCTION and not of clock cycles (cycle-accurate). Both models can be integrated directly in a UVM testbench using the DPI interface.