In reply to ben@SystemVerilog.us:
Ok my coworker and I are scratching our heads on a subject related to this.
What we’ve done in the past is have “phantom models” that are highly coupled with the RTL state machine. E.g. The RTL got a command, and performed:
Read 0x1, Read 0x2, Write 0x1, Write 0x2.
our “model/predictor” would do the exact same thing.
Now, if the RTL changes at all, adds an extra write, or changes the order, the model is wrong.
I think our paradigm of performing checking, and building models is incorrect. It’s coupled too tightly to the implementation details. Agree?
I’m guessing the model needs to care more about FUNCTION, and less about IMPLEMENTATION.
Thoughts so far?