Checkers are currently supported in simulation by a few vendors. As of today, I don;t believe that there is a vendor who supports checkers in formal verification.
Question: Do you know if there is (are) a vendor who supports it in synthesis? By support, I mean ignore all checkers in synthesis, yet the tool does not choke because of the checker syntax.
Thanks,
In reply to ben@SystemVerilog.us:
On formal verification, it was confirmed to me that one vendor does support a subset of the SystemVerilog checker construct.