In reply to ben@SystemVerilog.us:
I apologize for not stating my requirements clearly. I just ran your code on EDA playground and got this error:
Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Dec 8 04:32 2021
“testbench.sv”, 28: m.ap_phase_aligned_90_degrees_chk: started at 10ns failed at 35ns
Offending ‘((t2 - t1) == half_time_period)’