Checker for frequency switching mux module

SystemVerilog
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1

Hi,

I am writing a checker for a frequency switcher module. Its working is very similar to that of a multiplexer where there are two inputs and a select line. The only differences are that it has a reset input and the output does not change instantaneously with change in select line/reset/input. It takes a few cycles to do that. The check as such is very simple- Verify that the output follows the input based on the select line.

My question is: How do I consider the case where an input to the switch might abruptly change frequency/ stop completely and the output would not change immediately as it takes a few cycles(assuming select line remains same throughout)? My checker is throwing errors in such scenarios so I want an approach on how to handle it.

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In reply to rideroftheblue:

The output doest not change instantaneously. what do you mean by that? There is some internal logic which has to do some kind of operation and then the output will change or is it based on fixed no of clock cycle delay, the output will change?

3

In reply to rag123:

The output will change after a fixed number of clock cycle delay.

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In reply to rideroftheblue:

Can you post a small example of the code that can be compiled and simulated?