Check the value of `define macro

SystemVerilog
2

In reply to kpkrishna:

One can use ifdef... endif to check whether the macro is defined or not. Moreover, one can use an optional generate block to test the value of macro/parameters.


module top();
  `ifdef MY_MACRO
    if(`MY_MACRO == 1) begin                   // If MY_MACRO is defined and value is 1
      initial $display("MY_MACRO equal to 1");
    end else begin                             // If MY_MACRO is defined and value is not 1
      initial $display("MY_MACRO not equal to 1");
    end
  `else 
      initial $display("MY_MACRO not defined");  // If MY_MACRO is not defined 
  `endif
endmodule

Here if MY_MACRO is defined and value is 1, then the first initial block will be executed.

Refer to this section for more information.