Check that a sequence does not occur within other sequence

SystemVerilog
2

In reply to Sustrak:

How can I impose that between B and C there isn’t another B in between ?
[Ben] I would use the “not” property operator.

 start_seq |->
  not(##[1:*] Bseq  ##[1:*] Bseq) and
  ##[1:*] Bseq ##[1:*] Cseq;

I didn’t look at your specific code.
This code may never finish because of the ##[1:*].
It would be best if this is constraint, like ##[1:50]
Ben systemverilog.us