Check syntax check execution

SystemVerilog
,
1

HI All,

consider an example:

  if ( value inside {0,1,2,3}) && 
        (flag1 == 0) ||  
        (value inside {5,6}) && 
        (flag2 == 1)
    	)begin

Here, value is 2:0 and can take any one value from 0 to 7.
For simplication, I am representing the above code as

if (  (exp1) &&
      (exp2) ||
      (exp3) &&
      (exp4)
   )

When exp1 is true, that is when value is between 0 and 3, exp3 cannot be true, that is we cannot check value for 5 or 6.
Checking of exp3 is incorrect here, like a redundant.

Kindly let me know if my understanding is correct or not.

Thannk You

2

In reply to Mahesh K:

I’m not sure what you mean by “incorrect” without knowing what the correct behavior should be. What happens if values is 7?