Changing clock frequency during simulation run

SystemVerilog
,
6

In reply to rkg_:


`timescale 1ps/1ps
interface clk_gen(clk);
  output bit clk;
  
  shortint half_cycle = 1000;
  
  initial begin
    clk = 0;
    forever #half_cycle clk = ~clk;
  end
  
  function void set_half_cycle(shortint c);
    if (half_cycle == 0) begin
      $display("Error - can't set clock half_cycle to 0");
    end
    else begin
      half_cycle = c;
    end
  endfunction
endinterface

module testbench();
  wire clk;
  
  clk_gen clk_gen0(clk);
  
  initial begin
    repeat (100) @(posedge clk);
    clk_gen0.set_half_cycle(500);
    repeat (100) @(posedge clk);
    clk_gen0.set_half_cycle(20);
    repeat (100) @(posedge clk);
    clk_gen0.set_half_cycle(200);
    repeat (100) @(posedge clk);
    $finish;
  end
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1);
  end
endmodule