Cell 'xxx' cannot be found in liblist for binding instance 'xxx'

Dear friends,
I ran into some issues while trying to use pcie vip, I would appreciate if someone could provide some ideas to solve the problem.

I set up an environment according to the manual, but when I compile it, I get an error.The error is as follows.

Error-[CFCILFBI] Cannot find cell in liblist
../vip_instance/u_pcie_vip.sv, 5
  Cell 'svt_pcie_single_port_device_agent_hdl' cannot be found in liblist for 
  binding instance 'tb_top.spd_0'.
  Liblist: work
  Config rule: global default liblist
  Source Info: svt_pcie_single_port_device_agent_hdl spd_0(port_if_0);

But I have specified the library in the makefile and here is my configuration.

PCIE_VIP_PATH=../pcie_vip
PCIE_VIP ?=1

ifeq ($(PCIE_VIP),1)
	COMP_OPTS += +incdir+$(PCIE_VIP_PATH)/include/verilog
	COMP_OPTS += +incdir+$(PCIE_VIP_PATH)/include/sverilog
	COMP_OPTS += +incdir+$(PCIE_VIP_PATH)/src/sverilog/vcs
	COMP_OPTS += +incdir+$(PCIE_VIP_PATH)/src/verilog/vcs

	COMP_OPTS += +incdir+../RTL/config1/src/
	COMP_OPTS += +incdir+../RTL/config1/src/include/
	COMP_OPTS += +incdir+../RTL/config1/src/common

	COMP_OPTS += -y $(PCIE_VIP_PATH)/src/sverilog/vcs +libext+.sv
	COMP_OPTS += -y $(PCIE_VIP_PATH)/src/verilog/vcs +libext+.sv

	COMP_OPTS += +define+UVM_PKCKERR_MAX_BYTES=8192
	COMP_OPTS += +define+SNYOPSYS_SV
	COMP_OPTS += +define+SVT_PCIE_ENABLE_GEN4
	COMP_OPTS += +define+UVM_DISABLE_AUTO_ITEM_RECORDING  # just for uvm-1.1d

endif

I did a search on the system and found that the file does exist. Here are the results of my search.

ubuntu@ubuntu-virtual-machine:~/Desktop/work/PCIE_ver/tb$ grep -r -w "svt_pcie_single_port_device_agent_hdl"
pcie_vip/include/sverilog/svt_pciesvc_source.svi:`include `SVT_SOURCE_MAP_MODEL_MODULE(pcie_svt,pcie_device_agent_svt,O-2018.12,svt_pcie_single_port_device_agent_hdl)
pcie_vip/include/sverilog/svt_pcie_pipe_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_pipe_if 
pcie_vip/include/sverilog/svt_pcie_ext_clk_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_ext_clk_if  interface as one 
pcie_vip/include/sverilog/svt_pcie_snps_pipe_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_snps_pipe_if 
pcie_vip/include/sverilog/svt_pcie_pma_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_pma_if 
pcie_vip/include/sverilog/svt_pcie_app_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_app_if interface 
pcie_vip/include/sverilog/svt_pcie_snps_tunneled_pipe_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_snps_tunneled_pipe_if 
pcie_vip/include/sverilog/svt_pcie_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_if interface as its top-level interface. 
pcie_vip/include/sverilog/svt_pcie_if.svi: * svt_pcie_single_port_device_agent_hdl instance to class (run time component) svt_pcie_device_agent.  
pcie_vip/include/sverilog/svt_pcie_serdes_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_serdes_if  interface as one 
pcie_vip/include/sverilog/svt_pcie_pie8_eq_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_pie8_eq_if 
pcie_vip/include/sverilog/svt_pcie_pipe5_if.svi: * The unified VIP module svt_pcie_single_port_device_agent_hdl uses the svt_pcie_pipe5_if 
pcie_vip/src/sverilog/ncv/pciesvc_single_port_device.sv:module svt_pcie_single_port_device_agent_hdl(svt_pcie_if vip_port_if);   
pcie_vip/src/sverilog/vcs/pciesvc_single_port_device.sv:module svt_pcie_single_port_device_agent_hdl(svt_pcie_if vip_port_if);   
pcie_vip/src/sverilog/mti/pciesvc_single_port_device.sv:module svt_pcie_single_port_device_agent_hdl(svt_pcie_if vip_port_if);   
sim/compile.log:  Cell 'svt_pcie_single_port_device_agent_hdl' cannot be found in liblist for 
sim/compile.log:  Source Info: svt_pcie_single_port_device_agent_hdl spd_0(port_if_0);
vip_instance/hdl_interconnect_macros.sv:  svt_pcie_single_port_device_agent_hdl spd_``port_num``(port_if_``port_num``); \

I notice that this statement tells me that the module actually exists and is in the path.
But the error seems to be because it can’t be found.

pcie_vip/src/sverilog/vcs/pciesvc_single_port_device.sv:module svt_pcie_single_port_device_agent_hdl(svt_pcie_if vip_port_if);

This is very strange, because the lib path is specified with -y, but it doesn’t seem to work.
I would appreciate it if someone could help me find out the problem.

Best wishes.

This Siemens sponsored forum is not for tool related issues. Please refer to your tool documentation or contact your vendor support team for additional assistance.