In reply to shahkavish77:
Your code looks ok, except that I would write
@(posedge src_clk) $changed(data) ##1 @(dst_clk) (1)[*3];
// Basically use @(dst_clk) instead of @(edge dst_clk) since
// @(dst_clk) are the edges of dest_clk.
You need to simulate this.
Ben SystemVerilog.us