In reply to ben@SystemVerilog.us:
Thanks, Ben. My concept of ##1 got clear w.r.t clocking event.
Now in case, I want to satisfy requirement of checking stability of tx_data on tx_clk, modification in my previously provided code and overall property is correct?
sequence seq;
@(posedge src_clk) $changed(data) ##1 @(edge dst_clk) (1)[*3];
endsequence
property p1;
int d;
@(posedge src_clk) $changed(data) |=> stable(data) [*1:] ##1 (seq.matched,$display(“t=%t\n”,$time));
endproperty
assert property (p1);
Thanks,
Kavish