In reply to shahkavish77:
as ##1 means whole clock period only.
ap: assert property(@ (clocking_event1) (start_exp) |->
@ (clocking_event2) $stable(tx_data)[*3]);
Per 1800'2017 14.3 Clocking block declaration
clocking_event ::=
@ identifier
| @ ( event_expression )
Also, the $rose can include the clocking event.
$rose ( expression [, [clocking_event] ] )
Thus, the following is legal
property tx_data_check;
@(tx_clk)
(start_exp) |-> (@(rx_clk) $stable(tx_data)[*3])
endproperty
My SVA Handbook 4th Edition addresses multiclocking and its various rules. The following link is 4 pages from my book; it may clarify several issues.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment