Hi All,
I tried one solution on my end. It seems working, but not sure if any flaws. Can you please help finding any issue with it? Or better suggestions/other better solutions?
module m();
int data;
bit src_clk,dst_clk;
initial forever #5 src_clk=~src_clk;
initial forever #8 dst_clk=~dst_clk;
initial #10000 $finish();
initial begin : TB
@(posedge src_clk) data = 15;
repeat (1) @(posedge src_clk);
@(posedge src_clk) data = 24;
end
sequence seq; // Counts 3 edge of dst_clk after data changed on src_clk
@(posedge src_clk) $changed(data) ##1 @(edge dst_clk) (1) ##1 @(edge dst_clk)(1) ##1 @(edge dst_clk) (1);
endsequence
property p1; // checks data stability on src_clk until above seq gets completed.
int d;
@(posedge src_clk) $changed(data) |=> stable(data) [*1:] ##1 (seq.matched,$display(“t=%t\n”,$time));
endproperty
assert property (p1);
endmodule
Probable issue I see here is, display time t is in multiple of 5 (src_clk), I was expecting time t in multiple of 8(dst_clk), as seq.matched ends with @(edge dst_clk). Otherwise, I find this code working well for requirement.
Thanks,
Kavish