Casting into an enum

SystemVerilog
5

In reply to silverace99:

One can cast numbers to enums as I do here:


module cast;
	typedef bit[2:0] three_bits_t;
	typedef enum three_bits_t {
		ZERO = 0,
		ONE = 1,
		TWO = 2
	} four_e;


	four_e fe;

	initial
		for (three_bits_t ii = 0; ii <= 3; ii++) begin
			$cast(fe, ii);
			$display (fe.name());
		end
endmodule

I’ve never once looked at the UVM source code to debug a problem, so I’d assume that code is working properly.