Casting into an enum

SystemVerilog
4

In reply to raysalemi:

Thanks Ray. I assume by that code that it means you can’t directly cast or assign the 3-bit op to enum even though it is also a 3-bit variable?

Also, I recompiled and am still getting this niggling uvm_analysis_port $cast error, so there is evidently something else going on:

Error-[IATC] Illegal argument to $cast
/apps/vcsmx/etc/uvm-1.2/src/tlm1/uvm_analysis_port.svh, 74
  Illegal or unsupported arguments to $cast.
  Source info: $cast(__obj__, t)

I googled uvm_analysis_port.svh and if I’m right the error line references the analysis port write() function:

8   // Method: write
   69   // Send specified value to all connected interface
   70   function void write (input T t);
   71     uvm_tlm_if_base # (T, T) tif;
   72     for (int i = 0; i < this.size(); i++) begin
   73       tif = this.get_if (i);
   74       if ( tif == null )
   75         uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE);
   76       tif.write (t);
   77     end 
   78   endfunction

However I can’t tell where the $cast error comes into play.

For reference I’m doing all this on EDA Playground so the code is all visible: (2) - EDA Playground