In reply to ilia:
ilia,
The UVM is just SystemVerilog code organized into a package. The UVM factory creates objects by doing indirect calls to an objects constructor, new(), via a create() method. The create() method usually constructs the requested class type, but first checks to see if someone has applied an a type override setting, and constructs an object of that type instead. The overridden type is always a derived type of the requested type. So the create() method always returns an object who class type is the same as the requested type, or an extension of that class type. Once you have a handle to object, the standard SystemVerilog rules for inheritance and assignment to class variables apply.
I explain this in detail in my new SystemVerilog OOP for UVM Verification course.