Cast "this" operator

SystemVerilog
,
1

I am building an OOP testbench for some ethernet packet verification. I need to compute a checksum, and I would really like to be able to use the streaming operators to take my ethernet class and populate a queue. Something like this:

bit[15:0] checksum[$];
checksum = { >> {this} };
// compute the checksum with a loop here

The code above compiles just fine, but when I try to run it in ModelSim 10.3, I get the following error:

** Fatal: Casting is only allowed on bit stream types.

Time: 0 ns Iteration: 0 Process: /model_test/#INITIAL#5 File: …

It sounds like what I am trying to do is not supported. So my question is: Is there a way to cast a class into a queue or byte stream without manually placing all the class members into the queue?

Thanks.

2

This works for me in 10.3:

module top;
   bit [1:0] xy;
class A;
   bit 	     x=1;
   bit 	     y;
   function void stream();
      xy = {>>{this}};
   endfunction
endclass
   A a;
   initial begin
      a = new;
      a.stream;
      $displayb(xy);
   end
endmodule

However, I do not recommend using a class handle as bit-stream type because there is no way to control which members are part of the bitstream, and in the long run you will which you had explicitly listed the members you wanted. There will always be certain members you do not want as part of the stream, especially if you are using a base class library like the UVM which has inherited members like “m_name” that you would not want in the stream.