Capture time between two events for multiple cycle

SystemVerilog
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I need to calculate the average time to complete a write/read activity. Lets say there is a bus signal,hwrite. hwrite high->Write, hwrite Low->Read. Certain write/read operation can take 3 cycle,other takes 2,other maybe 10 and so on. I would like to calculate what’s the average latency of a write/read cycle.
So I need to calculate the time between hwrite-high and the next hwrite low, add to a queue or some other array and repeat the same for all the write/read .

At the end of all the cycle,I’ll calculate the time taken by all the writes/read divided by number of write/read. Can someone please suggest me a way to achieve it. I am not able to capture the time correctly. Any suggestion would be great.

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In reply to Spriyada29:
You can use assertions with function calls (or just tasks) to update read and write counters.
Basically, you update a read_count and write_count with the number of cycles it took to complete the transaction, and do a sample. See my paper on tasks and assertions.
https://verificationacademy.com/forums/systemverilog/vf-horizonspaper-sva-alternative-complex-assertions#reply-66770

You can also consider the use of covergroup and binning for your statistics. From my SVA Handbook, 4th Edition the example may give you ideas.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

3

Of course, you can use queues to push the values of the counts, and and end of test pop and add, then divide by the queue depth as you suggested.
Ben systemverilog.us