Can't understand how covergroup sample works

UVM
,
18

it doesn’t work

class calc_scoreboard extends  uvm_subscriber #(calc_trans);

`uvm_component_utils(calc_scoreboard)
 logic[0:7] a;
 logic[0:7] b;
 logic[0:3] opcode;
 int res;
 bit error;
 bit wrong_result;

function new (string name, uvm_component parent);
	super.new(name, parent);
  cover_bus=new;
  
endfunction : new

 function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction: build_phase
 
  covergroup cover_bus;
 coverpoint opcode {bins _add={0}; bins _sub={1}; bins _mult ={2}; bins _div={3}; }
coverpoint b {bins zero={0};}
option.at_least = 1;
 endgroup:cover_bus 

virtual function void write (calc_trans t);
  a=t.a;
  b=t.b;
  opcode=t.opcode;
  res=t.res;
  error=t.error;
  cover_bus.sample();