Can you use a radix to print readable names in Verilog (or SystemVerilog)?

SystemVerilog
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2

In reply to SparkyNZ:

I recommend using an enumeration in your code. You can then use the .name() function to print the value of the variable:


module test();
  typedef enum bit [2:0] {
    LOAD_REG, REFRESH, PRECHARGE, ACTIVE, WRITE, READ, BURST_TERM, NOP
  } CMD_RAM_t;

  CMD_RAM_t cmd;

  initial begin
    cmd = REFRESH;
    $display("Command is %s", cmd.name());
    cmd = WRITE;
    $display("Command is %s", cmd.name());
    cmd = BURST_TERM;
    $display("Command is %s", cmd.name());
  end
endmodule

You could also create an associative array as shown here, but it isn’t as efficient.