Can we use $rose along with posedge clk

SystemVerilog
4

In reply to dvuvmsv:

  property p1;
    //@(posedge clk) $rose(a) |-> ##2 $rose(b);
    //@(posedge clk) a |-> b;
  endproperty

Hi Dave,
Instead of using $rose(a) just using a will result in the same output.
Do we really need $rose(a)
Thanks,
JeffD.