Can we use $rose(a) along with @posedge clk. $rose is checking for rising edge of signal a.
If we include @(posedge clk) and then check $rose(a) will it create a problem ?
module tb;
logic a=0,b=0,c=0,clk=0;
initial
forever #10 clk = ~clk;
property p1;
@(posedge clk) $rose(a) |-> ##2 $rose(b);
endproperty
assert property (p1)
$display("Assertion Passed");
else
$display("Assertion Failed");
initial
begin
@(posedge clk);
a=1;b=0;c=0;
repeat(2) @(posedge clk);
a=0;b=1;c=0;
repeat(2) @(posedge clk);
a=0;b=0;c=1;
#100;
$finish;
end
initial
begin
$dumpvars;
$dumpfile("tb.vcd");
end
endmodule
Thanks,
JeffD
In reply to dvuvmsv:
Please use code tags making your code easier to read. I have added them for you.
$rose and $fell are sampled value functions. They looking for state transitions from the previous posedge clk to the current posedge. It is not looking for a @(posedge a).
In reply to dvuvmsv:
property p1;
//@(posedge clk) $rose(a) |-> ##2 $rose(b);
//@(posedge clk) a |-> b;
endproperty
Hi Dave,
Instead of using $rose(a) just using a will result in the same output.
Do we really need $rose(a)
Thanks,
JeffD.
In reply to dvuvmsv:
In reply to dvuvmsv:
property p1;
//@(posedge clk) $rose(a) |-> ##2 $rose(b);
//@(posedge clk) a |-> b;
endproperty
Hi Dave,
Instead of using $rose(a) just using a will result in the same output.
Do we really need $rose(a)
Thanks,
JeffD.
It depends on protocol check. If its level signal , then it does not make sense to use $rose. However if it needs to been checked on every transition of 0->1 should be in asserted in certain clock cycle, then its better to use $rose. All depend on requirement , and check.