Can we use internal signal of DUT while writing the assertion property

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Thanks Ben :)

let me reframe my question in slightly diffrent way :-

  • lets say design has output signal inc and dec. i need to write property where I have to use inc and dec signal. and condition is like if inc or dec happen consecutively 4 times lock will be de- asserted

  • But in DUT they have used internal signal(fll_unlock_check_timer) to detect inc or dec. and every inc or dec fll_unlock check timer will change.

So my question is, Can i directly use (fll_unlock_check_timer == 4) lock should be de-asserted ?