Can we delare variables with `define

SystemVerilog
,
1

declaration
[`define interface_no vifh_1] //is it a valid syntax if valid how to check that vifh_1 is defined .how to find which interface_no is assigned …

in driver :
@(negedge interface_no.TxWordClkHS) // will interface_no replace with vifh_1…?
interface_no.TxALPCodeHS0<=1; @(negedge interface_no.TxWordClkHS)
`interface_no.TxALPCodeHS0<=0;

for example : define width 2 //when ever i use width it will be replaced by 2
define width ab // if i use width will it replace with ab ??

i was tring to replace a variable with other variable for a particular condition …

2

In reply to rahulraoece:

`define is a pre-processor macro. When the compiler pre-processes your source file, it will do a simple text substitution, then compile the resulting file.

Have you tried what you wanted to do? Did you get errors? Was the compiler doing something unexpected?