Can normal args change the value of a object out of function

The following task, I think a_item_h will be copied to t.
and the change of t will not have effect to a_item_h .
but actually a_item_h changed to the value set by the task.
I think task set_item( int a,int b, ref a_item t); will act like this.
Can anyone help me on this,thanks.


class a_item extends uvm_sequence_item;
	rand bit [7:0] a_data;
	rand bit [7:0] b_data;
	`uvm_object_utils_begin(a_item)
		`uvm_field_int(a_data,UVM_ALL_ON)
		`uvm_field_int(b_data,UVM_ALL_ON)
	`uvm_object_utils_end	
	function new(string name="a_item");
		super.new(name);
	endfunction
endclass

class a_seq_base extends uvm_sequence;
	`uvm_object_utils(a_seq_base)
	a_item a_item_h;
	int a;
	int b;

	function new(string name="a_seq_base");
		super.new(name);
	endfunction
	virtual task body();
		`uvm_fatal(get_type_name(),"MUST override this class")
	endtask
endclass

class a_seq extends a_seq_base;
	`uvm_object_utils(a_seq)
	function new(string name="a_seq");
		super.new(name);
	endfunction

	task set_item( int a,int b, a_item t);
		t.a_data = a;
		t.b_data = b;
	endtask

	virtual task body();
		uvm_sequence_item tmp;
		tmp =create_item(a_item::get_type(),m_sequencer,"req");

		void'($cast(a_item_h,tmp));
		start_item(a_item_h);
		a_item_h.randomize();
		a_item_h.a_data = a;
		a_item_h.b_data = b;
			$display("--a_seq body0----$$$$$");
		//set_item(a_item_h,10,100);
		set_item(10,100,a_item_h);
		`uvm_info(get_name(),$sformatf("%s",a_item_h.sprint()),UVM_LOW)
			$display("--a_seq body1----$$$$$");
		finish_item(a_item_h);
		
	endtask
endclass

In reply to designer007:

Please see my course on SystemVerilog OOP.