In reply to dave_59:
Hi Dave,
My requirement is that the memory data agent should put data on the same clock edge when the RTL (DUT) generate write enable. Since there is no flexibility to provide data on a later clock edges, I am mimicking DUT functionality in interface. Hence the interface also generates write enables as DUT and these are used by driver and monitor. My thoughts behind choosing interface for this are:
1. The monitor also should know when to capture the data (especially when the agent is passive).
2. Similarly the driver should know when to drive the data.
3. Since both the driver and monitor dependent on write enable, I have chosen interface to generate this.
4. By mimicking DUT behavior, I am not relying on write enable generated by DUT. Hence there is a scope to detect misbehavior of DUT for write enable also.
5. The interface works in active region same as DUT and hence there wouldn’t be any possibility for race condition.
My understanding is that “slave sequence” link suggested by you doesn’t work for this requirement as I have to respond on the same clock edge. Please comment.
Thanks,
Santhosh