In reply to santhoshr30:
You have not described your situation very clearly. First you say the write_enable is given by the DUT. (I assume that means the DUT is driving the write_enable) And then you say you need to generate the write_enable in the SystemVerilog interface. And is the memory part of the BFM, or in another agent. You may want to look at : Sequences/Slave | Verification Academy