Can I use ">>" on the configure function in RAL model?

UVM
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3

In reply to chr_sue:

In reply to UVM_LOVE:
It’s your code you are showing here. You should know what your objection is.
8’hA>>0 means you do not shift anything.

 addr_reg_type extends uvm_reg;                
            
  rand uvm_reg_field addr;
          
  virtual function void build();                    
    addr = uvm_reg_field::type_id::create("addr");  
    addr.configure(this, 4, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h2>>0, 1, 1, 1);
    add_hdl_path_slice("addr_reg", 0, 4);
    addr.set_reset(`UVM_REG_DATA_WIDTH'h3>>0, "SOFT");   
    uvm_pkg::uvm_resource_db#(bit)::set({"REG::",get_full_name()}, "NORMAL", 1);
    wr_cg.set_inst_name($sformatf("%s.wcov", get_full_name()));
    rd_cg.set_inst_name($sformatf("%s.rcov", get_full_name()));
  endfunction

Sir,

I came across

 uvm_pkg::uvm_resource_db#(bit)::set({"REG::",get_full_name()}, "NORMAL", 1);

Could you please help me to understand what the usage this is?

For example, uvm_resource_db#(int)::set(“uvm_test_top.env”, “my_int”, 1024); is good for readability.
But uvm_pkg::uvm_resource_db#(bit)::set({“REG::”,get_full_name()}, “NORMAL”, 1); is don’t know what does this mean.