In reply to ben@SystemVerilog.us:
@ben. thanks for the update. i figured that and reran it is working now. what i wasnt sure is my approach to saving the variable on first clock and then using them to compare on different clock. and since my clk is faster than clk_out i will have more than one instance of assertion triggered (4 in this case) will that create an issue with storing local variable. but i tested it out looks like it will work.
i had to make minor adjustment to implement to match spec
property req_to_out_chk;
logic [19:0] addr_l;
logic [11:0] apid_l;
@(posedge CLK) ((start === 1’b1),addr_l=reg_addr,apid_l=ap_id)
|=>##0 @(posedge CLK_OUT) (1) [*4:10] ##1( (start_out == 1) && (addr_out == addr_l) && (ap_id_out == apid_l) );