Can i save variables when assertion is triggered and then use them to check the consequence?

SystemVerilog
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2

In reply to shahparth08:

@(posedge CLK) disable iff(~resetb)…
Thus, resetb is a reset signal that goes from 0 to 1.
Assertion is disabled when resetb==0.

 
@(posedge CLK) disable iff(~resetb) ((start === 1'b1),addr_l=reg_addr,apid_l=ap_id) ##1 @(posedge CLK_OUT) (~resetb) [*4]|=>... 
//If (~resetb==0) the assertion is disabled, thus never fires. 
// Since you are trying to test the after effect of a reset, you need to delete the disable. Thus, 

property req_to_out_chk;
logic [19:0] addr_l;
logic [11:0] apid_l;

@(posedge CLK) ((start === 1'b1),addr_l=reg_addr,apid_l=ap_id) ##1 @(posedge CLK_OUT) (~resetb) [*4]
|=>( (start_out == 1) && (addr_out == addr_l) && (ap_id_out == apid_l) );
endproperty
// BTW, arethe clocks working at startup?

Ben Cohen
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