Can i read signal rise edge at clock positive edge

SystemVerilog
1

Hi all , is there a way i can read the signal is high (rising edge) at the same clock cycle postive edge ? , i always read it one in the next clock but i want to read it high with the 1st clock positive edge as in the picture

2

In reply to bassem yasser:

You would have a race condition if you try to read the updated value, and that’s not how real hardware works. You can try reading it one the negative edge the clock.