Can I put an assert statement inside of a task?

SystemVerilog
6

In reply to ianmurph:

We really can’t help more without seeing how the signals in your interface get their values. (i.e. are there any race conditions that might affect how you think the values should be interpreted?)

You could write a similar piece of behavioral code

always begin
    @(posedge axis_clk iff m_axis_tuser_sof)
    $display("antecedent happens",, $time);
    repeat(4) @(posedge axis_clk)
    if(m_axis_tlast)
      $display("assertion should have passed");
    else
      $display("assertion should have failed");
end

If this co