In reply to ianmurph:
Can you explain to me why this doesn’t work? It seems like assertion_error doesn’t get set - if I use a signal of type ‘bit’, it always prints ‘0’ to the console. If I use signal type ‘logic’ it always prints ‘x’ to the console.
No, I do not undersgtand that. However, I believe that you’ll get a lot of answers from my paper
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
I address your topic of writing assertions in interfaces and reading the violations or results in the class.
Definitely read that paper. From the paper:
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SVA handles cycle accurate checks more effectively than with an application using scoreboarding because the verification of the signals is done at every cycle rather than at the completion of the data gathering process. The action block of an assertion can modify SystemVerilog interface variables or static class variable on either a pass or a fail action of the assertion. Those variables can then be used by a class instance to drop an objection or to modify the flow of the class. Figure 2.0 demonstrates these concepts. Figure 2.0 Using the results of an assertion to stop the simulator3 http://SystemVerilog.us/verizons/sc2uvm.sv
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Ben