Can I put an assert statement inside of a task?

SystemVerilog
4

In reply to ben@SystemVerilog.us:

Thanks for the reply. I am reading your paper now, but emulating the concurrent assertion using a task might be a bit over my head. I could leave it in the interface file, but we are using a scoreboard to monitor pass/fails, so I might just stick to immediate assertions.

I attempted a workaround where the assertion in the interface sets an error bit, and then I try to read that error bit from my task inside my testcase class, but this doesn’t work. Can you explain to me why this doesn’t work? It seems like assertion_error doesn’t get set - if I use a signal of type ‘bit’, it always prints ‘0’ to the console. If I use signal type ‘logic’ it always prints ‘x’ to the console.

Assertion inside interface file:

	//Assertions
	
	bit assertion_error;
	
	// m_axis_tlast should go high WINDOW_SIZE_X - 1 clock cycles after m_axis_tuser_sof
	property TLAST_FLAG;
		@(posedge axis_aclk) (m_axis_tuser_sof |-> ##4 m_axis_tlast);
	endproperty
	assert_tlast_flag: assert property (TLAST_FLAG) assertion_error = 0;
	else assertion_error = 1;

endinterface

Reading the error bit inside my testcase class task:

		$display("The value of assertion_error is: %0b", vpattgen_if.assertion_error);	
      end
   endtask