Can I pass parameters down

SystemVerilog
, , ,
7

In reply to dave_59:

Dave, I have a coverage module using the parameter to declare the signals, the compilation failed by “The use of a non-constant expression to override a parameter value is illegal”. There are a few modules in our env using the parameter the way in your above example and have no issue, so not sure if the failure is due to the parameter used in the signal declaration. How to fix the error?

Here is the simplified code.


module module_cov #(int ENTRIES, int NUM) (
  input logic [ENTRIES-1:0] rd_q,
  input logic [ENTRIES-1:0] rd_buf [NUM-1:0]
  );
endmodule

module module_rtl #(parameter ENTRIES = 8, parameter NUM = 2) (
  input logic [ENTRIES-1:0] read_q,
  input logic [ENTRIES-1:0] read_buf [NUM-1:0]
  ); 
endmodule : module_rtl

module top;
  ...
  
  bind 'RTL_PATH module_cov #(.ENTRIES('RTL_PATH.ENTRIES), .NUM('RTL_PATH.NUM)) module_cov_inst (
    .rd_q   ('RTL_PATH.read_q),
    .rd_buf ('RTL_PATH.read_buf)
  );
endmodule : top