Can I multiply real number with bit signed [15:0]?

SystemVerilog
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1

Can I multiply real number with bit signed [15:0]?

2

In reply to saritr:

Here its exaxmple

http://sandbox.mc.edu/~bennet/cs110/flt/dtof.html

3

In reply to saritr:

module test;

bit signed [15:0] a = -10;

real b;

initial
begin
b = 3 * a;
$display(" value of a is “,a);
$display(” value of b is %f ",b);
end

endmodule