Can I force a signal accross packages?

SystemVerilog
1

Hi all,

 I need to force signals in DUT in my tests, however my tests are packed in a package, so I can't use "$root.a.b..." to force signals directly, is there a solution? thx!
2

Add an interface class to your package

interface class abstract_forces;
// this could be parameterized and accept arguments.
  pure virtual function void apply_forces;
endclass

Create a module that has the functions that do the forces to the DUT, and inside that module, construct a concrete class that could can add via the config_db and call from your test.

module DUT_forces;
import uvm_pkg::*;
import test_pkg::*;

function void forceset1;
  force $root.a.b.c = 0;
  force $root.d.e.f = 0;
endfunction

class concrete_set1 implements abstract_forces;
  virtual function void apply_forces;
    forceset1;
  endfunction
endclass
concrete_set1 h1 = new();
initial uvm_config_db#(DUT_api)::set(null,"*","set1",h1);

function void forceset2;
  force $root.g.h.i = 0;
  force $root.j.k.l = 0;
endfunction

class concrete_set2 implements abstract_forces;
  virtual function void apply_forces;
    forceset1;
  endfunction
endclass
concrete_set2 h2 = new();
initial uvm_config_db#(abstract)::set(null,"*,"set2",h2);
endmodule

Then in your test class, you get the concrete class object and call the forces() method

class test extends uvm_test;

abstract_forces f_h;

function void build_phase(uvm_phase);

 if( !uvm_config_db #(abstract_forces)::get( this , "" , "set1" , f_h; ) ) begin
      `uvm_error(...)
    end
endfunction
task run_phase(uvm_phase phase);

  f_h.apply_forces;
endtask

endclass :test
3

In reply to dave_59:

Thanks Dave! I 'll try it.