I have a systemverilog module. This module have a lot of always @* blocks. I am just starting out with systemverilog and I am wondering that is there any particular reason that those blocks cannot be put together as just 1 always @* block?
In reply to aryajur:
You can put those blocks together as just 1 always @* block.
The reason you don’t is because partitioning/clustering groups of
functionality related logic makes the code more
maintainable and readable.
Would you really want to group together some arithmetic logic
with a bus interface logic?
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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