Can cover bins be created for all data types in SV?

Coverage
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1

I am creating coverbins for a variable.

Declaring variable in config file:

real time sig_delay;

Later in the monitor:

delay: coverpoint cfg.sig_delay{
bins min_val = {280ns};
bins max_val = {650ns};
}

Whereby I’m getting the following error:

Illegal use of a real number as part of a constant expression [4(IEEE)].

Is there any way of preserving the fact that I have to give ns as the unit of the bin value, and still achieve this?

2

In reply to ambreezesj:

There are two separate issues here. First is that currently, coverpoints and their bins only handle integral expressions. Although there has been some effort in the IEEE committee and with vendors to accept real expressions, nothing has been standardized yet. And floating point arithmetic issues will likely prevent you binning specific values due to rounding errors. You will more likely have to specify ranges. You handle this now by casting your bins with
int’(280ns).

But the other problem is dealing with timescales. You need to be careful that the timescales used when defining the covergroup match the timescale used in capturing the sig_delay. SystemVerilog does not do this automatically for you.

3

One more alternative is to create the additional logic expression and cover the outputs of expression. This can allow the real number coverage.

One of the way:
bit value_max;
assign value_max = (sig_delay == 650.00);

max_delay: coverpoint value_max {
bins true_value = {1};
}