Can anyone suggest how to write following assertion

[Have_A_Doubt]

@Deep_learn_R
You asked this question already
Solve the following assertion - SystemVerilog - Verification Academy

@Deep_learn_R

I tried this, is it correct way ? please suggest
$rose(REQ) |-> ##3 $rose(GRANT)##0 ($stable(GRANT) throughout REQ)

Have you tested your code ? Did the output match your expectations ?