Can any one help me to generate a clock of 300mhz in system verilog test bench

SystemVerilog
1

Hi, I’m beginner in system verilog, i got a situation to generate a clock of 300 MHz from test bench can any one help with the code. Thanks in advance.

2

In reply to chakrik:
Is a close approximation ok?
300MHz has a period of 3.333 with the clock toggling every 1.66666ns

 bit clk3; 
 initial forever #1.67 clk3 = !clk3;